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JTAG
The following figure provides the boundary-scan timing diagram.
JTAG
External Clock
Boundary
Data Inputs
Boundary
Data Outputs
Boundary
Data Outputs
VM
t JTKLDV
t JTKLDX
t JTKLDZ
Output Data Valid
t JTDVKH
VM
t JTDXKH
Input
Data Valid
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 42. Boundary-Scan timing diagram
The following figure provides the test access port timing diagram.
JTAG
External Clock
TDI, TMS
TDO
TDO
VM
t JTKLOV
t JTKLOX
t JTKLOZ
Output Data Valid
t JTIVKH
VM
t JTIXKH
Input
Data Valid
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 43. Test access port timing diagram
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
51
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